The present invention relates to a semiconductor integrated device, and more particularly to a reference voltage generator for generating a reference voltage having a constant voltage level.
In semiconductor integrated devices, it is very important to stably maintain an internal operational voltage so as to ensure operational stability and reliability of semiconductor integrated elements. Particularly, there should be a reference voltage generator for generating a reference voltage having a constant voltage level so that an interior of a chip is not influenced according to the variation of an external power voltage and so that the semiconductor integrated device is stably operated. Such a reference voltage generator is especially required in the semiconductor integrated devices which operate using a low power voltage. Obtaining a reference voltage from the reference voltage generator that does not have a very large deviation is difficult not only due to variation of the eternal power voltage, but also variation of temperature and manufacturing processes semiconductor integrated devices.
FIG. 1 is a view showing a reference voltage generator according to the conventional art. The reference voltage generator includes a resistance 5 formed between the power voltage VCC inputted from outside and a node N1 and an NMOS transistor 10 formed between the node N1 and a ground voltage VSS. In FIG. 1, a drain terminal and a gate terminal of the NMOS transistor 10 are connected to the node N I so as to be controlled by the reference voltage Vref.
With reference to FIGS. 1 and 2, the operation of the reference voltage generator according to the conventional art will be explained. Current I1 and 12 flowing into the resistance 5 and the NMOS transistor 10 are shown in FIG. 2 where the reference voltage Vref is generated as a voltage V1. When the power voltage VCC externally inputted is at the high level during operating the reference voltage generator of FIG. 1, the current I1 flowing into the resistance 5 is increased and a potential at the node N1 is raised. Since the node N1 is connected to the gate terminal of the NMOS transistor 10, the NMOS transistor 10 is turned on. Thereby, the current I2 flows into a channel of the transistor 10 to raise the potential of the reference voltage Vref.
On the other hand, when the power voltage VCC externally inputted is at the low level, the current I1 flowing into the resistance 5 is reduced and the potential at the node N 1 is dropped. However, since the node N1 is connected to the gate terminal of the NMOS transistor 10, the current I2 flows into the NMOS transistor 10 to relatively drop the potential of the reference voltage Vref. As mentioned above, in all the two cases that the power voltage VCC inputted is at the high level or low level, the reference Vref is raised or dropped according to the variation of the power voltage inputted.
Therefore, there arises a disadvantage that the reference voltage Vref with respect to the power voltage VCC is not stable. In the operation of the reference generator of FIG. 1, the current I1 is changed to I1', I1", I2 and I2" according to the characteristic of the resistance 5 or the transistor 10 due to the influence on the manufacturing process of the semiconductor integrated device. At a result, the reference voltage Vref is also changed to V1' and V2". Further, it is difficult to maintain the reference voltage Vref at a constant level, since the resistance 5 or the transistor 10 forming the reference voltage generator shown in FIG. 1 sensitively operate in accordance with variation of the temperature.
FIG. 3 is a view showing another reference voltage generator according to the conventional art. The reference voltage generator shown in FIG. 3 includes an N-channel depletion transistor 15 formed between the power voltage VCC inputted from outside and a node N2 and an N-channel depletion transistor 20 formed between the node N2 and the ground voltage VSS. The gate terminals of the N-channel depletion transistors 15 and 20 are connected to the ground voltage VSS, respectively.
The reference voltage generator of FIG. 3 will be explained in detail with reference to FIG. 4, which shows the relationship between voltage and current. In the reference voltage generator of FIG. 3, the current flowing into the N-channel transistors 15 and 20 is represented as I3 and I4. In such case, the reference voltage Vref is designated as a voltage V2. However, the current flowing into the N-channel depletion transistors 15 and 20 is changed to I3', I3", I4' and I4" according to the variation of temperature and the manufacturing process of the semiconductor integrated device. Thus, it is difficult to maintain the reference voltage Vref at constant level.
FIG. 5 is a view showing another reference generator according to the conventional art. FIG. 6 is a view showing the relationship between the reference voltage and the power voltage of FIG. 5. The reference voltage generator shown in FIG. 5 is comprised of a resistance 25 formed between the power voltage VCC and a node N3; a resistance 30 formed between the node N3 and a node N4; and NMOS transistors 35 and 40 connected between the node N4 and the ground voltage VSS. A gate terminal of a PMOS transistor 45 is connected to the node N4, a source terminal thereof to the reference Vref, and a drain terminal thereof to a source terminal of the NMOS transistor 40. Further, the gate terminal of the NMOS transistor 40 is coupled to the power voltage VCC.
The operation of FIG. 5 will be explained in detail with reference to FIG. 6, which shows the relationship between the reference voltage and the power voltage. If the reference voltage VCC having the constant voltage level is inputted to the reference voltage generator, the reference voltage Vref is clamped. In a case that the power voltage VCC is at the high level during the operation of the reference voltage generator shown in FIG. 5, the potential at the node N3 is raised, and the NMOS transistor 35 is then turned on. Thereby, the potential at the node N4 is dropped, and the PMOS transistor 45 is then turned on. Accordingly, the potential of the reference voltage Vref is dropped to be maintained at constant level because the potential at the node 3 is relatively dropped.
Meanwhile, in the other case that the power voltage VCC is at the low level, the potential at the node N3 is dropped, and the current flowing into the ground voltage from the NMOS transistors 35 and 45 is then reduced. Hence, the potential of the reference voltage Vref is kept at the constant level.
As shown in FIG. 6, when the power voltage VCC is linearly raised, the reference Vref must be kept at the constant value. However, the reference voltage Vref is changed to Vref' and Vref" due to a problem according to temperature and the manufacturing process of the semiconductor integrated device. Such deviation results from the variations of threshold voltages and resistance elements for each of the transistors.
Therefore, the reference voltage generator according to the conventional art can not generate the reference voltage having the constant voltage level owing to the variations of the power voltage externally inputted and the reference voltage in accordance with the manufacturing process of the semiconductor integrated device and temperature deviation. Thereby, there is much influence on the operational stability and reliability in the semiconductor integrated device.